Functional testing of the operation of digital circuits is generally implemented through the use of scan chains. A scan chain is typically composed of a chain of latches (e.g., flip flops) that are coupled to an input and an output of a digital circuit.
To test a digital circuit, a test input of known values, for example, a pre-determined string of “1”'s and “0”'s, are first serially scanned (or loaded) into a scan chain. The test input is transferred from the scan chain into the digital circuit, and propagated through the digital circuit. If there is a defect in the digital circuit, an incorrect result will be recovered from an output of the digital circuit. Common defects in digital circuits include faults such as stuck-at faults—e.g., stuck-at “0” or stuck-at “1”.
A typical problem associated with scan chains is that incorrect values may be loaded into a scan chain—e.g., due to a defect in a latch associated with the scan chain. The incorrect values within a scan chain can degrade testing performance of digital circuits.
Accordingly, what is needed is an improved technique that permits testing for the correct operation of digital circuitry—even when a scan chain includes one or more defective latches. The present invention addresses such a need.